View IR3081MPBF_8924908.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ir3081pbf page 1 of 40 10/01 /04 data sheet xphase tm vr 10 control ic description the ir3081pbf control ic combined with an ir xphase tm phase ic provides a full featured and flexible way to implement a complete vr 10 power solution. t he control ic provides overall system control and interfaces with any number of phase ics which each drive and monitor a single phase of a multiphase converter. the x phase tm architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. the ir3081pbf is intended for vrd or vrm/evrd 10 applications that use external vccvid/vtt circuits. features ? 6 bit vr 10 compatible vid with 0.5% overall system accuracy ? 1 to x phases operation with matching phase ics ? programmable dynamic vid slew rate ? no discharge of output capacitors during dynamic vid step-down (can be disabled) ? +/-300mv differential remote sense ? programmable 150khz to 1mhz oscillator ? programmable vid offset and load line output impedance ? programmable softstart ? programmable hiccup over-current protecti on with delay to prevent false triggering ? simplified powergood provides indication of proper operation and avoids false triggering ? operates from 12v input wi th 9.1v under-voltage lockout ? 6.8v/5ma bias regulator provides system reference voltage ? enable input ? small thermally enhanced 28l mlpq package package pinout n/c 27 ocset 15 iin 16 vdrp 17 fb 18 eaout 19 bbfb 20 vbias 21 vcc 22 lgnd 23 rmpout 24 enable 28 rosc 13 ss/del 25 vdac 14 trm4 12 trm3 11 vosns- 10 trm2 9 trm1 8 pwrgd 26 vid4 7 vid3 6 vid2 5 vid1 4 vid0 3 vid5 2 oscds 1 ir3081control ic downloaded from: http:///
ir3081pbf page 2 of 40 10/01 /04 ordering inforamation device order quantity IR3081MPBFtr 3000 per reel IR3081MPBF 100 piece strips absolute maximum ratings operating junction temperature..150 o c storage temperature range.-65 o c to 150 o c esd ratinghbm class 1c jedec standard pin # pin name v max v min i source i sink 1 oscds 20v -0.3v 1ma 1ma 2-7 vid0-5 20v -0.3v 10ma 10ma 8, 9, 11,12 trm1-4 do not connect do not conn ect do not connect do not connect 10 vosns- 0.5v -0.5v 10ma 10ma 13 rosc 20v -0.5v 1ma 1ma 14 vdac 20v -0.3v 1ma 1ma 15 ocset 20v -0.3v 1ma 1ma 16 iin 20v -0.3v 1ma 1ma 17 vdrp 20v -0.3v 5ma 5ma 18 fb 20v -0.3v 1ma 1ma 19 eaout 10v -0.3v 10ma 20ma 20 bbfb 20v -0.3v 1ma 1ma 21 vbias 20v -0.3v 1ma 1ma 22 vcc 20v -0.3v 1ma 50ma 23 lgnd n/a n/a 50ma 1ma 24 rmpout 20v -0.3v 1ma 1ma 25 ss/del 20v -0.3v 1ma 1ma 26 pwrgd 20v -0.3v 1ma 20ma 27 n/c n/a n/a n/a n/a 28 enable 20v -0.3v 1ma 1ma downloaded from: http:///
ir3081pbf page 3 of 40 10/01 /04 electrical specifications unless otherwise specified, thes e specifications apply over: 9.5v v cc 14v, 0 o c t j 100 o c parameter test condition min typ max unit vdac reference system set-point accuracy -0.3v vosns- 0.3v, connect fb to eaout, measure v(eaout) C v(vosns-) deviation from table 1. applies to all vid codes. 0.5 % source current r rosc = 41.9k ? 68 80 92 a sink current r rosc = 41.9k ? 47 55 63 a vid input threshold 500 600 700 mv vid input bias current 0v vid0-5 vcc -5 0 5 a regulation detect comparator input offset -5 0 5 mv regulation detect to eaout delay 130 200 ns bbfb to fb bias current ratio 0.95 1.00 1.05 a/ a vid 11111x blanking delay measure time till pwrgd drives low 800 ns vid step down detect blanking time measure from vid inputs to eaout 1.7 s vid down bb clamp voltage percent of vdac voltage 70 75 80 % vid down bb clamp current 3.5 6.2 12 ma error amplifier input offset voltage connect fb to eaout, measure v(eaout) C v(dac). from table 1. applies to all vid codes and -0.3v vosns- 0.3v. note 2 -3 4 8 mv fb bias current r rosc = 41.9k ? -31 -29.5 -28 a dc gain note 1 90 100 105 db gain-bandwidth product note 1 4 7 mhz source current 0.4 0.6 0.8 ma sink current 0.7 1.2 1.7 ma max voltage vbiasCveaout (refer enced to vbias) 125 250 375 mv min voltage normal operation or fault mode 30 100 150 mv vdrp buffer amplifier input offset voltage v(vdrp) C v(iin), 0.8v v(iin) 5.5v -8 0 8 mv input voltage range 0.8 5.5 v bandwidth (-3db) note 1 1 6 mhz slew rate 10 v/ s iin bias current -2.0 -0.75 0 a downloaded from: http:///
ir3081pbf page 4 of 40 10/01 /04 parameter test condition min typ max unit oscillator switching frequency r rosc = 41.9k ? 255 300 345 khz peak voltage (5v typical, measured as % of vbias) r rosc = 41.9k ? 70 71 74 % valley voltage (1v typical, measured as % of vbias) r rosc = 41.9k ? 11 14 16 % vbias regulator output voltage -5ma i(vbias) 0 6.5 6.8 7.1 v current limit -30 -15 -6 ma soft start and delay ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.85 1.3 1.5 v charge current 40 70 100 a discharge current 4 6 9 a charge/discharge current ratio 10 11.5 13 a/ a charge voltage 3.7 4.0 4.2 v delay comparator threshold relative to charge voltage 70 90 110 mv discharge comparator threshold 150 200 250 mv over-current comparator input offset voltage 1v v(ocset) 5v -10 0 10 mv ocset bias current r rosc = 41.9k ? -31 -29.5 -28 a pwrgd output output voltage i(pwrgd) = 4ma 150 400 mv leakage current v(pwrgd) = 5.5v 0 10 a enable input threshold voltage 500 600 700 mv bias current 0v v(enable) vcc -5 0 5 a vcc under-voltage lockout start threshold 8.6 9.1 9.6 v stop threshold 8.4 8.9 9.4 v hysteresis start C stop 150 200 300 mv general vcc supply current 8 11 14 ma vosns- current -0.3v vosns- 0.3v, all vid codes -5.5 -4.5 -3.5 ma note 1: guaranteed by design, but not tested in production note 2: vdac output is trimmed to compensate for error amplifier input offsets errors downloaded from: http:///
ir3081pbf page 5 of 40 10/01 /04 pin description pin# pin symbol pin description 1 oscds apply a voltage greater than vbias to disable the oscillator. used during factory testing & trimming. ground or l eave open for normal operation. 2-7 vid0-5 inputs to vid d to a converter 8, 9, 11,12 trm1-4 used for precision post-package trimmi ng of the vdac voltage. do not make any connection to these pins. 10 vosns- remote sense input. connect to ground at the load. 13 rosc connect a resistor to vosns- to program oscillator frequency and fb, ocset, bbfb, and vdac bias currents 14 vdac regulated voltage programmed by the vid inputs. current sensing and pwm operation are referenced to this pin. connect an external rc network to vosns- to program dynamic vid slew rate. 15 ocset programs the hiccup over-current thre shold through an external resistor tied to vdac and an internal current source. ov er-current protection can be disabled by connecting this pin to a dc voltage no greater than 6.5v (do not float this pin as improper operation will occur). 16 iin current sense input from the phase ic(s ). to ensure proper operation bias to at least 250mv (dont float this pin). 17 vdrp buffered iin signal. connect an external rc network to fb to program converter output impedance 18 fb inverting input to the error amplifier. converter output voltage is offset from the vdac voltage through an external resistor connected to the converter output voltage at the load and an internal current source. 19 eaout output of the error amplifier 20 bbfb input to the regulation detect comparator. connect to converter output voltage and vdrp pin through resistor network to program recovery from vid step-down. connect to ground to disable body braking tm during transition to a lower vid code. 21 vbias 6.8v/5ma regulated output used as a sys tem reference voltage for internal circuitry and the phase ics. 22 vcc power for internal circuitry 23 lgnd local ground and ic substrate connection 24 rmpout oscillator output voltage. used by phase ics to program phase delay 25 ss/del controls converter softstart, power good, and over-current delay timing. connect an external capacitor to lgnd to program the timing. an optional resistor can be added in series with the capacitor to reduce the over-current delay time. 26 pwrgd open collector output that drives low during softstart and any external fault condition. connect external pull-up. 27 n/c no internal connection 28 enable enable input. a logic low applied to this pin puts the ic into fault mode. downloaded from: http:///
ir3081pbf page 6 of 40 10/01 /04 system theory of operation xphase tm architecture the xphase tm architecture is designed for multiphase interlea ved buck converters which are used in applications requiring small size, design flexibility, low voltage, high cu rrent and fast transient response. the architecture can control converters of any pha se number where flexibility fa cilitates the design trade-off of multiphase converters. the scalable architecture can be applied to other applications which require high current or multiple output voltages. as shown in figure 1, the xphase tm architecture consists of a control ic and a scalable array of phase converters each using a single phase ic. the control ic communicates with the phase ics through a 5-wire analog bus, i.e. bias voltage, phase timing, average curr ent, error amplifier output, and vid volta ge. the control ic incorporates all the system functions, i.e. vid, pwm ramp oscillator, error amplifier, bias voltage, and fault protections etc. the phase ic implements the functions requir ed by the converter of each phase, i. e. the gate drivers, pwm comparator and latch, over-voltage protection, and current sensing and sharing. there is no unused or redundant silicon with the xphase tm architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. pcb layout is easier since the 5 wire bus eliminates the need for point-to-point wiring between the control ic and each phase. the critical gate drive and current sense connections are short and local to the phas e ics. this improves the pcb layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. 0.1uf cin ccs rcs ccs rcs 0.1uf vout+ vout sense- vout- 12v vid3 vid0 vid2 vid4 vout sense+ power good vr hot enable vid1 vid5 phase fault iru3081control ic >> bias voltage>> phase timing >> pwm control << current sense additional phases input/output iru3086phase ic control bus cout current sharecurrent share iru3086phase ic >> vid voltage phase faultphase fault phase hotphase hot figure 1. system block diagram downloaded from: http:///
ir3081pbf page 7 of 40 10/01 /04 pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 2. feed-forward voltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. an external rc circuit connected to the input voltage and ground is used to program the slope of the pwm ramp and to provide the feed-forward control at each phase. the pwm ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. +- 10k + - share adjust error amplifier current sense amplifier x34 x 0.91 20mv + - + - +- 10k share adjust error amplifier current sense amplifier x34 20mv x 0.91 + - + - + - + - + - dacin pwmrmp biasin rampin- rampin+ gateh scomp ishare csin+ gatel eain csin- system reference voltage enable clock pulse generator body braking comparator ramp discharge clamp pwm latch s reset dominant phase ic r pwm comparator rdrp rpwmrmp rphs2 cscomp + - rphs1 + - + - rcs rvfb + - cpwmrmp cscomp ccs rpwmrmp rcs +- cpwmrmp + - +- ccs rphs2 rphs1 + - gnd vout biasin vdac vbias dacin pwmrmp rampin+ vosns- vosns+ vosns- ishare rampin- iin vdrp eain gateh scomp csin- csin+ gatel eaout rmpout vin fb irosc system reference voltage vdac body braking comparator ramp discharge clamp enable clock pulse generator vbias regulator ifb vdrp amp 50% duty cycle ramp generator vvalley vpeak error amp r s reset dominant pwm latch phase ic cout control ic pwm comparator figure 2. pwm block diagram frequency and phase timing control the oscillator is located in the control ic and its freq uency is programmable from 150 khz to 1mhz by an external resistor. the output of the oscillator is a 50% duty cycl e triangle waveform with peak and valley voltages of approximately 5v and 1v respectively. this signal is used to program both the switching frequency and phase timing of the phase ics. the phase ic is programmed by resistor divider r phs1 and r phs2 connected between the vbias reference voltage and the phase ic lgnd pin. a co mparator in the phase ics detects the crossing of the oscillator waveform over the voltage gener ated by the resistor divider and triggers a clock pulse that starts the pwm cycle. the peak and valley voltages track the vbias vo ltage reducing potential phase ic timing errors. figure 3 shows the phase timing for an 8 phase converter. note that both slopes of the triangle waveform can be used for phase timing by swapping the rmpin+ and rmpinC pins, as shown in figure 2. downloaded from: http:///
ir3081pbf page 8 of 40 10/01 /04 ramp (fromcontrol ic) clk1 vvalley (1.00v) phase ic clock pulses vphase1&8 (1.5v) vphase3&6 (3.5v) vphase2&7 (2.5v) vphase4&5 (4.5v) vpeak (5.0v) clk2 50% rampduty cycle clk3clk4 clk5 clk6 clk7 clk8 slope = 80mv / % dc slope = 1.6mv / ns @ 200khz slope = 8.0mv / ns @ 1mhz figure 3. 8 phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon re ceiving a clock pulse, the pwm latch is set; the pwmrmp voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the non- overlap time. when the pwmrmp voltage exceeds the error amplifiers output voltage, the pwm latch is reset. this turns off the high side driver and then turns on the lo w side driver after the non-overlap time; it activates the ramp discharge clamp, which quickly discharges the pw mrmp capacitor to the vdac voltage of the control ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the common mode input range of the pwm comparator results in 100% duty cycle regardless of the voltage of the pwm ramp. this arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. the inductor current will increase much more rapidly than decrease in response to load transients. this control method is designed to provide single cycle transient response where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of the archit ecture is that differences in ground or input voltage at the phases have no effect on operation since the pwm ramps are referenced to vdac. figure 4 depicts pwm operating waveforms under various conditions. downloaded from: http:///
ir3081pbf page 9 of 40 10/01 /04 91% vdac phase ic clock pulse vdac eain pwmrmp gatel gateh duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid=11111x) figure 4. pwm operating waveforms body braking tm in a conventional synchronous buck conver ter, the minimum time required to redu ce the current in the inductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. the switch node voltage is then forced to decr ease until conduction of the synchronous rectifiers body diode occu rs. this increases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often higher th an output voltage, the inductor current slew rate can be increased by 2x or more. this patent pending technique is referred to as body braking and is accomplished through the 0% duty cycle comparator located in the ph ase ic. if the error amplifiers output voltage drops below 91% of the vdac voltage this comparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a series resist or and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in figure 5. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chosen so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current through l, and the sense circuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. downloaded from: http:///
ir3081pbf page 10 of 40 10/01 /04 c o l r l r cs c cs v o current sense amp csout i l v l v cs c figure 5. inductor current sensing and current sense amplifier the advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. the output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in series with the inductor, this is the only sense method that can support a single cy cle transient response. other methods provide no information during eit her load increase (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all additional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier is located in the phase ic, as shown in figure 5. its gain decreases with increasing temperature and is nominally 34 at 25oc and 29 at 125oc (-1470 ppm/oc). this reduction of gain tends to compensate the 3850 ppm/oc increase in inductor dcr. since in most designs the phase ic junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. the current sense amplifier can accept positive differ ential input up to 100mv and negative up to -20mv before clipping. the output of the current sense amplifier is su mmed with the dac voltage and sent to the control ic and other phases through an on-chip 10k ? resistor connected to the ishare pi n. the ishare pins of all the phases are tied together and the voltage on the share bus represent s the average current through all the inductors and is used by the control ic for voltage posit ioning and current limit protection. average current share loop current sharing between phases of the converter is achiev ed by the average current share loop in each phase ic. the output of the current sense amplifier is compared with the share bus less a 20mv offset. if current in a phase is smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces the slope of its pwm ramp thereby increasing its duty cy cle and output current. the crossover frequency of the current share loop can be programmed with a capacitor at the scomp pin so that the share loop does not interact with the output voltage loop. downloaded from: http:///
ir3081pbf page 11 of 40 10/01 /04 ir3081pbf theory of operation block diagram the block diagram of the ir3081pbf is shown in figure 6, and specific features are discussed in the following sections. erroramp ifb 1.3v vid = 11111x vidcontrol vid dac output vid step-down 6ua 50% duty cycle on 1.2v idischg 1.0v currentsource generator ramp generator 70ua ss/deldischarge iocset occomparator 6.8v vchg4v softstartclamp 5.0v vbiasregulator ichg vdrpamp rosc buffer amp 0.2v off 90mv 0.6v vcc uvlocomparator 9.1v + enablecomparator start 8.9v + - stop - delaycomparator dischargecomparator overcurrent faultlatch r s setdominant +- + - +- +- + - +- + - +- +- +- + - + +- + - + - + - + - iin vid3 vid5 vosns- vdac ocset lgnd vid2 vid4 rmpout ss/del rosc vid1 pwrgd vdrp vbias vid0 fb enable vcc bbfb eaout irosc irosc vbias irosc irosc disable irosc irosc irosc irosc irosc irosc irosc irosc figure 6. ir3081pbf block diagram vid control a 6-bit vid voltage compatible with vr 10, as shown in table 1, is available at the vdac pin. a detailed block diagram of the vid control circuitry can be found in figur e 7. the vid pins require an external bias voltage and should not be floated. the vid input comparators, with 0. 6v reference, monitor the vid pins and control the 6 bit digital-to-analog converter (dac) whose output is sent to the vdac buffer amplifier. the output of the buffer amplifier is the vdac pin. the vdac voltage is post-pack age trimmed to compensate for the input offsets of the error amplifier to provide a 0.5% system set-point accuracy. the actual vdac voltage does not determine the system accuracy and has a wider tolerance. downloaded from: http:///
ir3081pbf page 12 of 40 10/01 /04 the ir3081pbf can accept changes in the vid code wh ile operating and vary the dac voltage accordingly. the sink/source capability of the vdac buffe r amplifier is programmed by the same external resistor that sets the oscillator frequency. the slew rate of the voltage at the vdac pin can be adjus ted by an external capacitor between vdac pin and the vosns- pin. a resistor connected in se ries with this capacitor is required to compensate the vdac buffer amplifier. digital vid transitions result in a smooth analog transition of the vdac voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. it is desirable to prevent negative induct or currents in response to a request for a lower vid code. negative current transforms the buck converter into a boost converter and tr ansfers energy from the output capacitors back into the input voltage. this energy can cause voltage spikes and da mage the silver box or other components unless they are specifically designed to handle it. furthermore, power is wasted during the transfer of energy from the output back to the input. the ir3081pbf includes circuitry that turns off both cont rol and synchronous mosfets in response to a lower vid code so that the load current instead of the inductor discharges the output capacitors. a lower vid code is detected by the vid step-down detect comparator which monitors t he fast output of the dac (plus 7mv for noise immunity) compared to the slow output of the vdac pin. if a dynamic vid step down is detected, the body brake latch is set and the output of the error amplifier is pulled down to 75% of the dac voltage by the vid body brake clamp. this triggers the body braking tm function which turns off both high side and low side drivers in the phase ics. the converters output voltage needs to be monitored and compared to the vdac voltage to determine when to resume normal operation. unfortunately, the voltage on t he fb pin can be pulled down by its compensation network during the sudden decrease in the error amplifiers output voltage so an additional pin bbfb is provided. the bbfb pin is connected to the converter output voltage and vdrp pin with resistors of the same value as on the fb pin and therefore provides an un-corrupted representation of converter output voltage. the regulation detect comparator compares the bbfb to the vdac voltage and rese ts the body brake latch releasing the error amplifiers output and allowing normal operation to resume. body braking tm during a transition to a lower vid code can be disabled by connecting the bbfb pin to ground. enable vid = 11111x detect to error amp irosc (from current source generator) +- + - +- + - +- + - + - vosns- vid5 vid3 vid4 vid2 eaout vid1 vid0 vdac bbfb 0.6v vid input comparators (1 of 6 shown) - digital to analog converter + vdac buffer amp isource isink "fast" vdac "slow" vdac vid down bb clamp 75% 7mv reset dominant s 1.7us blanking regulation detect comparator body brake latch r vid step-down detect comparator 800ns blanking ibbfb figure 7. vid control block diagram downloaded from: http:///
ir3081pbf page 13 of 40 10/01 /04 processor pins (0 = low, 1 = high) processor pins (0 = low, 1 = high) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) 0 1 0 1 0 0 0.8375 1 1 0 1 0 0 1.2125 0 1 0 0 1 1 0.8500 1 1 0 0 1 1 1.2250 0 1 0 0 1 0 0.8625 1 1 0 0 1 0 1.2375 0 1 0 0 0 1 0.8750 1 1 0 0 0 1 1.2500 0 1 0 0 0 0 0.8875 1 1 0 0 0 0 1.2625 0 0 1 1 1 1 0.9000 1 0 1 1 1 1 1.2750 0 0 1 1 1 0 0.9125 1 0 1 1 1 0 1.2875 0 0 1 1 0 1 0.9250 1 0 1 1 0 1 1.3000 0 0 1 1 0 0 0.9375 1 0 1 1 0 0 1.3125 0 0 1 0 1 1 0.9500 1 0 1 0 1 1 1.3250 0 0 1 0 1 0 0.9625 1 0 1 0 1 0 1.3375 0 0 1 0 0 1 0.9750 1 0 1 0 0 1 1.3500 0 0 1 0 0 0 0.9875 1 0 1 0 0 0 1.3625 0 0 0 1 1 1 1.0000 1 0 0 1 1 1 1.3750 0 0 0 1 1 0 1.0125 1 0 0 1 1 0 1.3875 0 0 0 1 0 1 1.0250 1 0 0 1 0 1 1.4000 0 0 0 1 0 0 1.0375 1 0 0 1 0 0 1.4125 0 0 0 0 1 1 1.0500 1 0 0 0 1 1 1.4250 0 0 0 0 1 0 1.0625 1 0 0 0 1 0 1.4375 0 0 0 0 0 1 1.0750 1 0 0 0 0 1 1.4500 0 0 0 0 0 0 1.0875 1 0 0 0 0 0 1.4625 1 1 1 1 1 1 off 4 0 1 1 1 1 1 1.4750 1 1 1 1 1 0 off 4 0 1 1 1 1 0 1.4875 1 1 1 1 0 1 1.1000 0 1 1 1 0 1 1.5000 1 1 1 1 0 0 1.1125 0 1 1 1 0 0 1.5125 1 1 1 0 1 1 1.1250 0 1 1 0 1 1 1.5250 1 1 1 0 1 0 1.1375 0 1 1 0 1 0 1.5375 1 1 1 0 0 1 1.1500 0 1 1 0 0 1 1.5500 1 1 1 0 0 0 1.1625 0 1 1 0 0 0 1.5625 1 1 0 1 1 1 1.1750 0 1 0 1 1 1 1.5750 1 1 0 1 1 0 1.1875 0 1 0 1 1 0 1.5875 1 1 0 1 0 1 1.2000 0 1 0 1 0 1 1.6000 note: 3. output disabled (fault mode) table 1. voltage identification (vid) adaptive voltage positioning adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load when it is drawing maximum current. the circuitry related to voltage positioning is shown in figure 8. resistor r fb is connected between the error amplifiers inve rting input pin fb and the converters output voltage. an internal current source whose value is progra mmed by the same external resistor that programs the oscillator frequency pumps current into t he fb pin. the error amplifier forces the converters output voltage lower to maintain a balance at its inputs. r fb is selected to program the desired amount of fixed offset voltage below the dac voltage. the voltage at the vdrp pin is a buffered version of t he share bus and represents the sum of the dac voltage and the average inductor current of all the phases. the vdrp pin is connected to the fb pin through the resistor r drp . since the error amplifier will force the loop to maintain fb to be equal to the vdac reference voltage, an additional current will flow into the fb pin equal to (vdrp-vdac) / r drp . when the load current increases, the adaptive positioning voltage increases accordingly. more current flows through the feedback resistor r fb , and makes the output voltage lower proportional to the load current. t he positioning voltage can be programmed by the resistor r drp so that the droop impedance produces the desired co nverter output impedance. the offset and slope of the converter output impedance are referenced to and therefore independent of the vdac voltage. downloaded from: http:///
ir3081pbf page 14 of 40 10/01 /04 csin- csin+ csin- v drp isha re phase ic ea out phase ic current sense a mplif ier isha re isha re isha re isha re ... ... iin vdac vdac fb vdac 10k + - rfb + - rdrp + - ifb 10k + - vo er r o r amplif ier current sense a mplif ier control ic v drp a mplif ier csin+ figure 8. adaptive voltage positioning inductor dcr temperature correction if the thermal compensation of the inductor dcr provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative tem perature coefficient (ntc) thermistor c an be used for additional correction. the thermistor should be placed close to the inductor a nd connected in parallel with the feedback resistor, as shown in figure 9. the resistor in series with the thermist or is used to reduce the nonlinearity of the thermistor. a similar network must be placed on the bbfb to ensure proper operation during a transition to a lower vid code with body braking tm . ea out iiniin er r o r a mplif ier control ic avp amplifier + - rfb ifb rfb2 vdac rdrp + - rt vo fb v drp figure 9. temperature co mpensation of inductor dcr remote voltage sensing to reduce the effect of impedance in the ground plane, the vosns- pin is used for remote sensing and connected directly to the load. the vdac voltage is referenced to vosn s- to avoid additional error terms or delay related to a separate differential amplifier. the capacitor connect ing the vdac and vosns- pins ensure that high speed transients are fed directly into t he error amplifier without delay. downloaded from: http:///
ir3081pbf page 15 of 40 10/01 /04 soft start, over-current fault delay, and hiccup mode the ir3081pbf has a programmable soft-start function to lim it the surge current during the converter start-up. a capacitor connected between the ss/del and lgnd pins controls soft start as well as over-current protection delay and hiccup mode timing. a charge current of 70ua and di scharge current of 6ua control the up slope and down slope of the voltage at the ss/del pin respectively. figure 10 depicts the various operating modes as controlle d by the ss/del function. if there is no fault, the ss/del pin will begin to be charged. the error amplifier output is clamped low until ss/del reaches 1.3v. the error amplifier will then regulate the converters output voltage to match the ss/del voltage less the 1.3v offset until it reaches the level determined by the vid inputs. the ss/del voltage continues to increase until it rises above 3.91v and allows the pwrgd signal to be asserted. ss/del finally settles at 4v, indicating the end of the soft start. under voltage lock out and vid=11111x faults as well as a low signal on the enable input immediately sets the fault latch causing ss/del to begin to discharge. the ss/del capacitor will continue to discharge down to 0.2v. if the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur. a delay is included if an over-current condition occurs afte r a successful soft start sequence. this is required since over-current conditions can occur as part of normal operation due to load transients or vid transitions. if an over- current fault occurs during nor mal operation it will initiate the discharge of the capacitor at ss/del but will not set the fault latch immediately. if the ov er-current condition persists long enough for the ss/del capacitor to discharge below the 90mv offset of the delay co mparator, the fault latch will be set pu lling the error amplifiers output low inhibiting switching in the phase ics and de-asserting the pwrgd signal. the ss/del capacitor will continue to discharge until it reaches 0.2v and the fault latch is reset allowing a normal soft start to occur. if an over-current condition is again encountered during the soft start cycl e the fault latch will be set without any delay and hiccup mode will begin. during hiccup mode the charge to discharge current ratio results in a fixed 7.9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. however, the hiccup frequency is determined by the load current and over-current set value. the over-current delay can be reduced by adding a resistor in series with the ss/del capacitor. the delay comparators offset voltage is reduced by the drop in t he resistor caused by the discharge current. the value of the series resistor should be 10k ? or less to avoid interference with the soft start function. if ss/del pin is pulled below 0.9v, the converter can be disabled. under voltage lockout (uvlo) the uvlo function monitors the ir3081pbfs vcc supp ly pin and ensures that ir3081pbf has a high enough voltage to power the internal circuit. the ir3081pbfs uv lo is set higher than the minimum operating voltage of compatible phase ics thus providing uvlo protection for them as well. during power-up the fault latch is reset when vcc exceeds 9.1v and there is no other fault. if the vc c voltage drops below 8.9v the fault latch will be set. for converters using a separate 5v supply for gate driver bias an external uvlo circuit can be added to prevent any operation until adequate voltage is present. a diode connected between the 5v supply and the ss/del pin provides a simple 5v uvlo function. over current protection (ocp) the current limit threshold is set by a resistor connec ted between the ocset and vdac pins. if the iin pin voltage, which is proportional to the average current plus da c voltage, exceeds the ocset voltage, the over-current protection is triggered. vid = 11111x fault vid codes of 111111 and 111110 will set the fault latch and dis able the error amplifier. an 800ns delay is provided to prevent a fault condition from oc curring during dynamic vid changes. downloaded from: http:///
ir3081pbf page 16 of 40 10/01 /04 hiccup over-current protection normal operation start-up vcc vout pwrgd 3.91v ss/del (12v) 8.9vuvlo power-down re-start after ocp ocp threshold ocp delay (vout changes due to load and vid changes) enable 1.3v (vcc gates fault mode) (enable gates fault mode) iout figure 10. operating waveforms power good output the pwrgd pin is an open-collector output and should be pull ed up to a voltage source through a resistor. during soft start, the pwrgd remains low until the output vo ltage is in regulation and ss/del is above 3.91v. the pwrgd pin becomes low if the fault latch is set. a high leve l at the pwrgd pin indicates that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification. output voltage regulation within the design limits can logically be assur ed however, assuming no component failure in the system. load current indicator output the vdrp pin voltage represents the av erage current of the converter plus the dac voltage. the load current information can be retrieved by a differential amplifier which subtracts the vdac vo ltage from the vdrp voltage. system reference voltage (vbias) the ir3081pbf supplies a 6.8v/5ma precision reference voltage from the vbias pin. the oscillator ramp amplitude tracks the vbias voltage, which should be used to program the phase ic trip points to minimize phase delay errors. enable input pulling the enable pin below 0.6v sets the fault latch. downloaded from: http:///
ir3081pbf page 17 of 40 10/01 /04 application information rcs+ dbst cbst dbst rcs+ cbst dbst rcs+ cbst 20k rbiasin rvcc rphase62 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086phase ic l oscds 1 vid5 2 vid0 3 vid1 4 vid2 5 vid3 6 vid4 7 pwrgd 26 trm1 8 trm2 9 vosns- 10 trm3 11 trm4 12 vdac 14 ss/del 25 rosc 13 enable 28 rmpout 24 lgnd 23 vcc 22 vbias 21 bbfb 20 eaout 19 fb 18 vdrp 17 iin 16 ocset 15 n/c 27 ir3081control ic rcs- cscomp rcs- l cvccl dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086phase ic ccp rfb1 rphase32 rbbdrp rpwmrmp cpwmrmp rshare cvcc rpwmrmp cin cscomp rpwmrmp cin cscomp ccs+ cvccl 20k rbiasin vgate cscomp rgate 20k rbiasin qgate dgat e rvdac cpwmrmp cvcc cvcc rphase11 rdrp rcp css/del cin 10 ohm rvcc cfb rphase31 ccs- cpwmrmp cpwmrmp rocset rvcc rphase42 rphase13 rpwmrmp ccs+ rphase33 cvcc rphase21 20k rbiasin rphase12 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086phase ic ccs- cvccl cscomp cin 20k rbiasin rphase41 rphase23 rfb rosc cdrp cvccl cvcc dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086phase ic cscomp ccs- ccp1 rphase43 rvcc rvcc rpwmrmp cpwmrmp dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086phase ic l rvcc cpwmrmp rbbfb 20k rbiasin cin 0.1uf ccs- dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086phase ic rpwmrmp rphase22 rphase52 rphase61 ccs+ rcs- rphase63 rphase53 rss/del dbst ccs+ rcs+ 0.1uf cvcc rcs- cbst cvccl l cvdac cvcc cin ccs+ rvcc l ccs+ rcs- ccs- 1nf l rcs- rphase51 cvccl ccs- rdrp1 vrhot powergood vout sense+ vout+ phase fault vout- vout sense- vid0 vid5 enable vid1 vid3 vid4 12v vid2 cout distributionimpedance dbst rcs+ cbst dbst rcs+ cbst figure 11. ir3081pbf/ir3086 six- phase vrm/evrd 10 converter downloaded from: http:///
ir3081pbf page 18 of 40 10/01 /04 design procedures - ir3081pbf and ir3086 chipset ir3081pbf external components oscillator resistor rosc the oscillator of ir3081pbf generates a triangle waveform to synchronize the phase ics, and the switching frequency of the each phase converter equals the oscillator frequency, which is set by the external resistor r osc according to the curve in figure 13. soft start capacitor c ss/del and resistor r ss/del because the capacitor c ss/del programs four different time parameters, i.e. soft start delay time, soft start time, over-current latch delay time, and power good delay time, they should be considered together while choosing c ss/del . the ss/del pin voltage controls the slew rate of the conv erter output voltage, as shown in figure 10. after the enable pin voltage rises above 0.6v, there is a soft-start delay time t ssdel, after which the error amplifier output is released to allow the soft start. the soft start time t ss represents the time during which converter voltage rises from zero to v o. t ss can be programmed by an external capacitor , which is determined by equation (1). o ss o ss chg del ss v t v t i c * 10* 70 * 6 / ? = = (1) once c ss/del is chosen, the soft start delay time t ssdel, the over-current fault latch delay time t ocdel , and the delay time t vccpg from output voltage (v o ) in regulation to power good are fixed and shown in equations (2), (3) and (4) respectively. 6 / / 10*70 3.1* 3.1* ? = = del ss chg del ss ssdel c i c t (2) 6 / / 10*6 09.0* 09.0* ? = = del ss dischg del ss ocdel c i c t (3) 6 / / 10*70 )3.1 91.3(* )3.1 91.3(* ? ? ? = ? ? = o del ss chg o del ss vccpg v c i v c t (4) if faster over-current protection is required, a re sistor in series with the soft start capacitor c ss/del can be used to reduce the over-current fault latch delay time t ocdel , and the resistor r ss/del is determined by equation (5). equation (1) for soft start capacitor c ss/del and equation (4) for power good delay time t vccpg are unchanged, while the equation for soft start delay time t ss/del (equation 2) is changed to equation (6). considering the worst case values of charge and discharge current, r ss/del should be no grater than 10k ? . 6 / 6 / / 10*6 10*6 09.0 * 09.0 ? ? ? ? = ? = del ss ocdel dischg del ss dischg ocdel del ss c t i c i t r (5) 6 6 / / / / 10*70 ) 10*70* 3.1(* ) 3.1(* ? ? ? = ? ? = del ss del ss chg chg del ss del ss ssdel r c i i r c t (6) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac down-slope sr down can be programmed by t he external capacitor c vdac as defined in equation (7), where i sink is the sink current of vdac pin as shown in figure 15. the resistor r vdac is used to compensate vdac circuit and is determined by equation (8). the slew rate of vdac up-slope sr up is proportional downloaded from: http:///
ir3081pbf page 19 of 40 10/01 /04 to that of vdac down-slope and is given by equation (9), where i source is the source current of vdac pin as shown in figure15. down sink vdac sr i c = (7) 2 15 10 2.3 5.0 vdac vdac c r ? ? + = (8) vdac source up c i sr = (9) over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c, and therefore the maximum inductor d cr can be calculated from equation (10), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t_ room respectively. )] ( 10* 3850 1[ _ 6 _ _ room max l room l max l t t r r ? ? + ? = ? (10) the current sense amplifier gain of ir3086 decreases with temperature at the rate of 1470 ppm/c, which compensates part of the inductor dcr increase. the phase ic die temperature is only a couple of degrees celsius higher than the pcb temperature due to the low thermal impedance of mlpq package. the minimum current sense amplifier gain at the maximum phase ic temperature t ic_max is calculated from equation (11). )] ( 10* 1470 1[ _ 6 _ _ room max ic room cs min cs t t g g ? ? ? ? = ? (11) the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the sum of input offset (v cs_ofst) of the amplifier itself and that cr eated by the amplifier input bias currents flowing through the current sense resistors r cs+ and r cs- . ? ? + + ? ? ? + = cs csin cs csin ofst cs tofst cs r i r i v v _ _ (12) the over current limit is set by the external resistor r ocset as defined in equation (13), where i limit is the required over current limit. i ocset, the bias current of ocset pin, changes with switching frequency setting resistor r osc and is determined by the curve in figure 14. k p is the ratio of inductor peak cu rrent over average current in each phase and is calculated from equation (14). ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1( [ _ _ _ ? + + ? ? = (13) n i f v l v v v k o sw i o o i p / )2 /( ) ( ? ? ? ? ? = (14) no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp a resistor between fb pin and the converter out put is used to create output voltage offset v o_nlofst, which is the difference between v dac voltage and output voltage at no load condit ion. adaptive voltage positioning further lowers the converter voltage by r o *i o, where r o is the required output impedance of the converter. r fb is not only determined by i fb , the current flowing out of fb pin as show n in figure 14, but also affected by the adaptive voltage positioning resistor r drp and total input offset voltage of current sense amplifiers. r fb and r drp are determined by (15) and (16) respectively. downloaded from: http:///
ir3081pbf page 20 of 40 10/01 /04 max l fb o tofst cs nlofst o max l fb r i r n v v r r _ _ _ _ ? ? ? ? ? = (15) o min cs max l fb drp r n g r r r ? ? ? = _ _ (16) body braking tm related resistors r bbfb and r bbdrp the body braking tm during dynamic vid can be disabled by conne cting bbfb pin to ground. if the feature is enabled, resistors r bbfb and r bbdrp are needed to restore the feedback voltage of the error amplifier after dynamic vid step down. usually r bbfb and r bbdrp are chosen to match r fb and r drp respectively . ir3086 external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp pwm ramp is generated by connecting the resistor r pwmrmp between a voltage source and pwmrmp pin as well as the capacitor c pwmrmp between pwmrmp and lgnd. choose the desired pwm ramp magnitude v ramp and the capacitor c pwmrmp in the range of 100pf and 470pf, and then calculate the resistor r pwmrmp from equation (17). to achieve feed-forward volt age mode control, the resistor r ramp should be connected to the input of the converter. )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = (17) inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs+ and capacitor c cs+ in parallel with the inductor are chosen to match the time constant of the induct or, and therefore the voltage across the capacitor c cs+ represents the inductor current. if the two time constants are not the same, the ac component of the capacitor voltage is different from that of the real inductor current. the time constant mismatch does not affect the average current sharing among the multip le phases, but affect the current signal ishare as well as the output voltage during the load current tran sient if adaptive voltage positioning is adopted. measure the inductance l and the inductor dc resistance r l . pre-select the capacitor c cs+ and calculate r cs+ as follows. + + = cs l cs c rl r (18) the bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across r cs+, which is equivalent to an input offset voltage of the curr ent sense amplifier. the offs et affects the accuracy of converter current signal ishare as well as the accura cy of the converter output voltage if adaptive voltage positioning is adopted. to reduce the offset voltage, a resistor r cs- should be added between the amplifier inverting input and the converter output . the resistor r cs- is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input. + ? + ? ? = cs csin csin cs r i i r (19) if r cs- is not used, r cs+ should be chosen so that the offset voltage is small enough. usually r cs+ should be less than 2 k ? and therefore a larger c cs+ value is needed. downloaded from: http:///
ir3081pbf page 21 of 40 10/01 /04 over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is proportional to the die temperature t j (oc) of phase ic. determine the relationship between the die temperature of phase ic and the temperature of the power converter according to the power loss, pcb layout and airflow etc, and then ca lculate hotset threshold voltage corresponding to the allowed maximum temperature from equation (20). 241 .1 * 10*73.4 3 + = ? j hotset t v (20) there are two ways to set the over temperature threshold, central setting and local setting. in the central setting, only one resistor divider is used, and the setting voltage is connected to hotset pins of all the phase ics. to reduce the influence of noise on the accuracy of over te mperature setting, a 0.1uf capacitor should be placed next to hotset pin of each phase ic. in the local setting, a resistor divider per phase is needed, and the setting voltage is connected to hotset pin of each phase. the 0.1uf decoupling capacitor is not necessary. use vbias as the reference voltage. if r hotset1 is pre-selected, r hotset2 can be calculated as follows. hotset bias hotset hotset hotset v v v r r ? ? = 1 2 (21) phase delay timing resistors r phase1 and r phase2 the phase delay of the interleaved multiphase converte r is programmed by the resistor divider connected at rmpin+ or rmpin- depending on which slope of the oscill ator ramp is used for the phase delay programming of phase ic, as shown in figure 3. if the upslope is used, rmpin+ pin of the phase ic shou ld be connected to rmpout pin of the control ic and rmpin- pin should be connected to the resistor divi der. when rmpout voltage is above the trip voltage at rmpin- pin, the pwm latch is set. gatel becomes lo w, and gateh becomes high after the non-overlap time. if down slope is used, rmpin- pin of the phase ic should be connected to rmpout pin of the control ic and rmpin+ pin should be connected to the resistor divider. when rmpout voltage is below the trip voltage at rmpin- pin, the pwm latch is set. gatel becomes lo w, and gateh becomes high after the non-overlap time. use vbias voltage as the reference for t he resistor divider since the oscillator ramp magnitude from control ic tracks vbias voltage. try to avoid both edges of the oscilla tor ramp for better noise immunity. determine the ratio of the programming resistors correspondi ng to the desired switching frequencies and phase numbers. if the resistor r phasex1 is pre-selected, the resistor r phasex2 is determined as: phasex phasex phasex phasex ra r ra r ? ? = 1 1 2 (22) combined over temperature and phase delay setting resistors r phase1 , r phase2 and r phase3 the over temperature setting re sistor divider can be combined with the phase delay resistor divider to save one resistor per phase. calculate the hotset threshold voltage v hotset corresponding to the allowed maximum temperature from equation (20). if the over temperature setting volt age is lower than the phase delay setting voltage, vbias*ra phasex , connect rmpin+ or rmpin- pin between r phasex1 and r phasex2, and connect hotset pin between r phasex2 and r phasex3 . pre-select r phasex1 , ) 1( *) ( 1 2 phasex bias phasex hotset bias phasex phasex ra v r v v ra r ? ? ? ? = (23) ) 1(* 1 3 phasex bias phasex hotset phasex ra v r v r ? ? = (24) downloaded from: http:///
ir3081pbf page 22 of 40 10/01 /04 if the over temperature setting voltage is higher than the phase delay setting voltage, vbias*ra phasex , connect hotset pin between r phasex1 and r phasex2 and connect rmpin+ or rmpin- between r phasex2 and r phasex3 respectively. pre-select r phasex1 , hotset bias phasex bias phasex hotset phasex v v r v ra v r ? ? ? ? = 1 2 ) ( (25) hotset bias phasex bias phasex phasex v v r v ra r ? ? = 1 3 * (26) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a 0.1uf to 1uf capacitor is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf-1uf decoupling capacitors are require d at vcc and vccl pins of phase ics. voltage loop compensation the adaptive voltage positioning (avp) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. like cu rrent mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the do uble poles of the power stage, which make the voltage loop compensation much easier. resistors r fb and r drp are chosen according to equations (15) and (16), and the selection of compensation types depends on the output capacitors used in the converter. for the applications using electrolytic, polymer or al- polymer capacitors and running at lower frequency, type ii compensation shown in figure 12(a) is usually enough. while for the applications using only ceramic capacitors and running at hi gher frequency, type iii compensation shown in figure 12(b) is preferred. for applications where avp is not required, the compensati on is the same as for the regular voltage mode control. for converter using polymer, al-polymer, and ceramic capacitors, which have much higher esr zero frequency, type iii compensation is required as shown in figure 12(b) with r drp and c drp removed. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 12. voltage loop compensation network type ii compensation for avp applications determine the compensation at no load, the worst case condi tion. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, and determine r cp and c cp from equations (27) and (28), where l e and c e are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. downloaded from: http:///
ir3081pbf page 23 of 40 10/01 /04 2 2 ) * * * 2( 1 * ) 2( c c o pwmrmp fb e e c cp r c f v v r c l f r + ? ? ? ? ? = (27) cp e e cp r c l c ? ? = 10 (28) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation for avp applications determine the compensation at no load, the worst case cond ition. assume the time cons tant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by equations (29) and (30), where r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f ? ? = * * 2 1 (29) 180 )5.0 tan( 90 1 ? ? = a c (30) choose the desired crossover frequency fc around fc1 es timated by equation (29) or choose fc between 1/10 and 1/5 of the switching frequency per phase, and select the comp onents to ensure the slope of close loop gain is -20db /dec around the crossover frequency. choose resistor r fb1 according to equation (31), and determine c fb and r drp from equations (32) and (33). fb fb r r 2 1 1 = to fb fb r r 3 2 1 = (31) 1 4 1 fb c fb r f c ? ? = (32) drp fb fb fb drp r c r r c ? + = ) ( 1 (33) r cp and c cp have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. determine r cp and c cp from equations (34) and (35). o pwmrmp fb e e c cp v v r c l f r ? ? ? ? ? = 2 ) 2( (34) cp e e cp r c l c ? ? = 10 (35) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation for non-avp applications resistor r fb is chosen according to equations (15), and resistor r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of the sw itching frequency per phase and select the desired phase margin c. calculate k factor from equation (36), and determi ne the component values based on equations (37) to (41), )]5.1 180 ( 4 tan[ + ? = c k (36) downloaded from: http:///
ir3081pbf page 24 of 40 10/01 /04 k v v f c l r r o pwmrmp c e e fb cp ? ? ? ? ? ? = 2 ) 2( (37) cp c cp r f k c ? ? = 2 (38) cp c cp r k f c ? ? ? = 2 1 1 (39) fb c fb r f k c ? ? = 2 (40) fb c fb c k f r ? ? ? = 2 1 1 (41) current share loop compensation the crossover frequency of the current s hare loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. a capacitor from scomp to ground is usually enough for the share loop compensation. choose the crossover frequency of current share loop (f ci ) based on the crossover frequency of voltage loop (f c), and determine the c scomp , 6 _ 10*05.1* 2 *)] (* * * 2 1[* * * * * *65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? + = (42) where f mi is the pwm gain in the current share loop , ) (*) ( * * * dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f ? ? ? = ( 43) downloaded from: http:///
ir3081pbf page 25 of 40 10/01 /04 design example 1 - vrm 10 2u converter specifications input voltage: v i =12 v dac voltage: v dac =1.35 v no load output voltage offset: v o_nlofst =20 mv output current: i o =105 adc maximum output current: i omax =120 adc output impedance: r o =0.91 m ? vcc ready to vcc power good delay: t vccpg =0-10ms soft start time: t ss =2 ms over current delay: t ocdel =0.5ms dynamic vid down-slope slew rate: sr down =2.5mv/us over temperature threshold: t pcb =115 oc power stage phase number: n=6 switching frequency: f sw =400 khz output inductors: l=220 nh, r l =0.47 m ? output capacitors: al-polymer, c=560uf, r c = 7m ? , number cn=10 ir3081pbf external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the curve in figure 13. for switching frequency of 400khz per phase, choose r osc =30.1k ? soft start capacitor c ss/del and resistor r ss/del because faster over-current protection is required, the soft start capacitor c ss/del in series with the resistor r ss/del is used. calculate the soft start capacitor from the required soft start time. uf v t i c o ss chg del ss 1.0 10*20 35.1 10*2 10*70 3 3 6 / = ? ? = ? = ? ? ? calculate the soft start resistor from the required over current delay time t ocdel , = ? ? = ? ? = ? ? ? ? k i c i t r dischg del ss dischg ocdel del ss 10 10*6 10*1.0 10*6 10*5.0 09.0 09.0 6 6 6 3 / / the soft start delay time is ms i i r c t chg chg del ss del ss ssdel 86.0 10*70 ) 10*70* 10*10 3.1( 10*1.0 ) 3.1( 6 6 3 6 / / = ? ? = ? ? ? = ? ? ? the power good delay time is ms i v c t chg o del ss vccpg 8.1 10*70 )3.1 33.1 91.3(* 10*1.0 )3.1 91.3(* 6 6 / = ? ? = ? ? = ? ? downloaded from: http:///
ir3081pbf page 26 of 40 10/01 /04 vdac slew rate programming capacitor c vdac and resistor r vdac from figure 15, the sink current of vdac pin corresponding to 400khz (r osc =30.1k ? ) is 76ua. calculate the vdac down-slope slew-rate programming capacitor from the required down-slope slew rate. nf sr i c down sink vdac 4.30 10/ 10*5.2 10*76 6 3 6 = = = ? ? ? , choose c vdac =33nf calculate the programming resistor. = + = + = ? ? ? 5.3 ) 10*33( 10*2.3 5.0 10*2.3 5.0 29 15 2 15 vdac vdac c r from figure 15, the source current of vdac pin is 110ua. the vdac up-slope slew rate is us mv c i sr vdac source up / 3.3 10*33 10* 110 9 6 = = = ? ? over current setting resistor r ocset the room temperature is 25oc and the target pcb temperat ure is 100 oc. the phase ic die temperature is about 1 oc higher than that of phase ic, and the induct or temperature is close to pcb temperature. calculate inductor dc resistance at 100 oc, = ? ? + ? = ? ? + ? = ? ? ? m t t r r room max l room l max l 61.0 )]25 100 ( 10* 3850 1[ 10*47.0 )] ( 10* 3850 1[ 6 3 _ 6 _ _ the current sense amplifier gain is 34 at 25oc, and its gain at 101oc is calculated as, 2.30 )] 25 101 ( 10* 1470 1[ 34 )] ( 10* 1470 1[ 6 _ 6 _ _ = ? ? ? ? = ? ? ? ? = ? ? room max ic room cs min cs t t g g set the over current limit at 135a. from fi gure 14, the bias current of ocset pin (i ocset ) is 41ua with r osc =30.1k ? . the total current sense amplifier input offset volt age is 0.55mv, which includes the offset created by the current sense amplifier input resistor mismatch. calculate constant k p, the ratio of inductor peak current ov er average current in each phase, 3.0 6/ 135 )2 10* 400 12 10* 220 /( 33.1)33.1 12( / )2 /( ) ( 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1( [ _ _ _ ? + + ? ? = = ? + ? ? = ? ? ? k 3.13 ) 10*41 /(2.30 ) 10*55.0 3.1 10*61.0 6 135 ( 6 3 3 no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp from figure 14, the bias current of fb pin is 41ua with r osc =30.1k ? . = ? ? ? ? ? = ? ? ? ? ? = ? ? ? ? ? ? 365 10* 61.0 10* 41 10* 91.0 6 10* 55.0 10* 20 10* 61.0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r = ? ? ? = ? ? ? = ? ? k r n g r r r o min cs max l fb drp 21.1 10*91.0 6 2.30 10*61.0 365 3 3 _ _ downloaded from: http:///
ir3081pbf page 27 of 40 10/01 /04 body braking related resistors r bbfb and r bbdrp n/a. the body braking during dynamic vid is disabled. ir3086 external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp set pwm ramp magnitude v pwmrmp =0.8v. choose 220pf for pwm ramp capacitor c pwmrmp , and calculate the resistor r pwmrmp , )] ln( ) [ln( pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? ? ? ? = = ? ? ? ? ? ? ? = ? k 1.16 )]8.0 35.1 12 ln( )35.1 12 [ln( 10* 220 10* 400 12 33.1 12 3 , choose r pwmrmp =16.2k ? inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- choose c cs+ =47nf, and calculate r cs+, = = = ? ? ? + + k c rl r cs l cs 0.10 10*47 ) 10*47.0/( 10* 220 9 3 9 the bias currents of csin+ and cs in- are 0.25ua and 0.4ua respec tively. calculate resistor r cs- , = ? = ? = + ? k r r cs cs 2.6 10*0.10 4.0 25.0 4.0 25.0 3 , choose r cs- =6.19k ? over temperature setting resistors r hotset1 and r hotset2 use central over-temperature setting and set the temperatur e threshold at 115 oc, which corresponds to the ic die temperature of 116 oc. calculate the hotset threshold voltage corresponding to the temperature thresholds. v t v j hotset 79.1 241 .1 116 10*73.4 241 .1 * 10*73.4 3 3 = + ? = + = ? ? pre-select r hotset1 =10.0k ? , = ? ? = ? ? = k v v v r r hotset bias hotset hotset hotset 57.3 79.1 8.6 79.1 10*10 3 1 2 phase delay timing resistors r phase1 and r phase2 use central over-temperature setting and set the temperatur e threshold at 115 oc, which corresponds to the ic die temperature of 116 oc. calculate the hotset threshold voltage corresponding to the temperature thresholds. the phase delay resistor ratios for phases 1 to 6 at 400khz of switching frequencies are ra phase1 =0.628, ra phase2 =0.415, ra phase3 =0.202, ra phase4 =0.246, ra phase5 =0.441 and ra phase6 =0.637 starting from down- slope. pre-select r phase11 =r phase21 =r phase31 =r phase41 =r phase51 = r phase61 =10k ? , = ? ? = ? ? = k r ra ra r phase phase phase phase 9.16 10*10 628 .0 1 628 .0 1 3 11 1 1 12 r phase22 =7.15k ? , r phase32 =2.55k ? , r phase42 =3.24k ? , p phase52 =7.87k ? , r phase62 =17.4k ? downloaded from: http:///
ir3081pbf page 28 of 40 10/01 /04 bootstrap capacitor c bst choose c bst =0.1uf decoupling capacitors for phase ic and power stage choose c vcc =0.1uf, c vccl =0.1uf voltage loop compensation type ii compensation is used for the converter with al-polymer output capacitors. choose the crossover frequency fc=40khz, which is 1/10 of the switchin g frequency per phase, and determine rcp and c cp . = + ? ? ? ? ? ? ? ? ? ? ? = + ? ? ? ? ? = ? ? ? ? ? k r c f v v r c l f r c c o ramp fb e e c cp 0.2 ) 10*7* 10* 560 * 10*40* 2(1*) 10 20 35.1( 8.0 365 )10 10 560 ()6/ 10 220 ( ) 10 40 2( ) * * * 2(1 * ) 2( 23 6 3 3 6 9 23 2 2 nf r c l c cp e e cp 71 10 0.2 )10* 10 560 ()6/ 10 220 ( 10 10 3 6 9 = ? ? ? ? ? = ? ? = ? ? , choose c cp =68nf choose c cp1 =47pf to reduce high frequency noise. current share loop compensation the crossover frequency of the current share loop f ci should be at least one decade lower than that of the voltage loop f c . choose the crossover frequency of current share loop f ci =4khz , and calculate c scomp , 011 .0 )35.1 12(*)35.1 8.0 12( 8.0* 10* 400 * 10* 220 * 10*2.16 ) (*) ( * * * 3 12 3 = ? ? ? = ? ? ? = ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10*05.1* 2 *)] (* * * 2 1[* * * * * *65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? + = 6 3 4 4 6 3 3 3 10*05.1* 10*4 2) 10*1.9* 105 33.1( 011 .0*] 105 ) 10*1.9* 105 33.1(*10* 10* 560 * 10*4* 2 1[*)6 10*47.0(*34* 105 *12* 10*2.16*65.0 ? ? ? ? + = ? ? ? ? nf 4.31 = choose c scomp =33nf. downloaded from: http:///
ir3081pbf page 29 of 40 10/01 /04 design example 2 - evrd 10 high frequency all-ce ramic converter specifications input voltage: v i =12 v dac voltage: v dac =1.3 v no load output voltage offset: v o_nlofst =20 mv output current: i o =105 adc maximum output current: i omax =120 adc output impedance: r o =0.91 m ? vcc ready to vcc power good delay: t vccpg =0-10ms soft start time: t ss =2.9ms over current delay: t ocdel =2.1ms dynamic vid down-slope slew rate: sr down =2.5mv/us over temperature threshold: t pcb =115 oc power stage phase number: n=6 switching frequency: f sw =800 khz output inductors: l=100 nh, r l =0.5 m ? output capacitors: ceramic, c=22uf, r c = 2m ? , number cn=62 ir3081pbf external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the curve in figure 13 data sheet. for switching frequency of 800khz per phase, choose r osc =13.3k ? soft start capacitor c ss/del and resistor r ss/del because faster over-current protection is required, the soft start capacitor c ss/del in series with the resistor r ss/del is used. calculate the soft start capacitor from the required soft start time. uf v t i c o ss chg del ss 16.0 10*20 3.1 10*9.2 10*70 3 3 6 / = ? ? = ? = ? ? ? , choose c ss/del =0.15uf calculate the soft start resistor from the required over current delay time t ocdel , = ? ? = ? ? = ? ? ? ? k i c i t r dischg del ss dischg ocdel del ss 1 10*6 10*15.0 10*6 10*1.2 09.0 09.0 6 6 6 3 / / the soft start delay time is ms i i r c t chg chg del ss del ss ssdel 6.2 10*70 ) 10*70* 10*1 3.1( 10*15.0 ) 3.1( 6 6 3 6 / / = ? ? = ? ? ? = ? ? ? the power good delay time is ms i v c t chg o del ss vccpg 85.2 10*70 )3.1 28.1 91.3(* 10*15.0 )3.1 91.3( 6 6 / = ? ? = ? ? ? = ? ? downloaded from: http:///
ir3081pbf page 30 of 40 10/01 /04 vdac slew rate programming capacitor c vdac and resistor r vdac from figure 15, the sink current of vdac pin corresponding to 800khz (r osc =13.3k ? ) is 170ua. calculate the vdac down-slope slew-rate programming capacitor from the required down-slope slew rate. nf sr i c down sink vdac 68 10/ 10*5.2 10* 170 6 3 6 = = = ? ? ? calculate the programming resistor. = + = + = ? ? ? 2.1 ) 10*68( 10*2.3 5.0 10*2.3 5.0 29 15 2 15 vdac vdac c r from figure 15, the source current of vdac pin is 250ua. the vdac up-slope slew rate is us mv c i sr vdac source up / 7.3 10*68 10* 250 9 6 = = = ? ? over current setting resistor r ocset the room temperature is 25oc and the target pcb temperat ure is 100 oc. the phase ic die temperature is about 1 oc higher than that of phase ic, and the induct or temperature is close to pcb temperature. calculate inductor dc resistance at 100 oc, = ? ? + ? = ? ? + ? = ? ? ? m t t r r room max l room l max l 64.0 )]25 100 ( 10* 3850 1[ 10*5.0 )] ( 10* 3850 1[ 6 3 _ 6 _ _ the current sense amplifier gain is 34 at 25oc, and its gain at 101oc is calculated as, 2.30 )] 25 101 ( 10* 1470 1[ 34 )] ( 10* 1470 1[ 6 _ 6 _ _ = ? ? ? ? = ? ? ? ? = ? ? room max ic room cs min cs t t g g set the over current limit at 135a. from fi gure 14, the bias current of ocset pin (i ocset ) is 90ua with r osc =13.3k ? . the total current sense amplifier input offset volt age is 0.55mv, which includes the offset created by the current sense amplifier input resistor mismatch. calculate constant k p, the ratio of inductor peak current ov er average current in each phase, 32.0 6/ 135 )2 10* 800 12 10* 100 /( 28.1)28.1 12( / )2 /( ) ( 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1( [ _ _ _ ? + + ? ? = = + ? ? = ? ? ? k 34.6 ) 10*90/(2.30*) 10*55.0 32.1 10*64.0 6 135 ( 6 3 3 no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp from figure 14, the bias current of fb pin is 90ua with r osc =13.3k ? . = ? ? ? ? = ? ? ? ? ? = ? ? ? ? ? ? 162 10*64.0* 10*90 10*91.0 6 10*55.0 10*20 10*64.0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r = ? ? = ? ? ? = ? ? 576 10*91.0 6 2.30* 10*64.0 162 3 3 _ _ o min cs max l fb drp r n g r r r downloaded from: http:///
ir3081pbf page 31 of 40 10/01 /04 body braking related resistors r bbfb and r bbdrp n/a. the body braking during dynamic vid is disabled. ir3086 external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp set pwm ramp magnitude v pwmrmp =0.75v. choose 100pf for pwm ramp capacitor c pwmrmp , and calculate the resistor r pwmrmp , )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = = ? ? ? ? ? ? ? ? = k 2.18 )]75.0 3.1 12 ln( )3.1 12 [ln( 12 10* 100 3 10* 800 12 28.1 inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- choose 47nf for capacitor c cs+, and calculate r cs+, = = = ? ? ? + + k c rl r cs l cs 22.4 10*47 ) 10*5.0/( 10* 100 9 3 9 the bias currents of csin+ and cs in- are 0.25ua and 0.4ua respec tively. calculate resistor r cs- , = ? = ? = + ? k r r cs cs 61.2 10*22.4 4.0 25.0 4.0 25.0 3 combined over temperature and phase delay setting resistors r phasex1 , r phasex2 and r phasex3 the over temperature setting resistor divider is combined wi th the phase delay resistor divider. set the temperature threshold at 115 oc, which corresponds to the ic die te mperature of 116 oc, and calculate the hotset threshold voltage corresponding to the temperature thresholds. v t v j hotset 79.1 241 .1 116 10*73.4 241 .1 10*73.4 3 3 = + ? = + ? = ? ? the phase delay resistor ratios for phases 1 to 6 at 800khz of switching frequencies are ra phase1 =0.665, ra phase2 =0.432, ra phase3 =0.198, ra phase4 =0.206, ra phase5 =0.401 and ra phase6 =0.597 starting from down- slope. the over temperature setting voltage of phases 1, 2, 5, and 6 is lower than the phase delay setting voltage, vbias*ra phasex. pre-select r phase11 =10k ? , = ? ? ? ? ? = ? ? ? ? = k ra v r v v ra r phasex bias phasex hotset bias phasex phasex 1.12 ) 665 .0 1(8.6 10*10 )79.1 8.6 665 .0( ) 1( *) ( 3 1 2 = ? ? = ? ? = k ra v r v r phasex bias phasex hotset phasex 87.7 ) 665 .0 1(*8.6 10*1.12 79.1 ) 1(* 3 1 3 r phase21 =10k ? , r phase22 =2.94k ? , r phase23 =4.64k ? r phase51 =10k ? , r phase52 =2.32k ? , r phase53 =4.42k ? r phase61 =10k ? , r phase62 =8.25k ? , r phase63 =6.49k ? downloaded from: http:///
ir3081pbf page 32 of 40 10/01 /04 the over temperature setting voltage of phases 3 a nd 4 is higher than the phase delay setting voltage, vbias*ra phasex. pre-select r phasex1 =10k ? , = ? ? ? ? = ? ? ? ? = 887 79.1 8.6 10*10 )8.6 198 .0 79.1( ) ( 3 31 3 32 hotset bias phase bias phase hotset phase v v r v ra v r = ? ? ? = ? ? = k v v r v ra r hotset bias phase bias phase phase 67.2 79.1 8.6 10*10 8.6 198 .0 * 3 31 3 33 r phase41 =10k ? , r phase42 =768 ? , r phase43 =2.80k ? bootstrap capacitor c bst choose c bst =0.1uf decoupling capacitors for phase ic and power stage choose c vcc =0.1uf, c vccl =0.1uf voltage loop compensation type iii compensation is used for the converter with only ceramic output capacitors. the crossover frequency and phase margin of the voltage loop can be estimated as follows. khz r r g c r f le fb cs e drp c 146 )6/ 10*5.0( 162 34 ) 10* 22 62( 2 576 2 3 6 1 = ? ? ? ? ? = ? ? ? ? = ? ? = ? ? = 63 180 )5.0 tan( 90 1 a c choose = ? = ? = 110 162 3 2 3 2 1 fb fb r r choose the desired crossover frequency fc (=14 0khz) around fc1 estimated above, and calculate nf r f c fb c fb 2.5 110 10* 140 4 1 4 1 3 1 = ? ? = ? ? = , choose c fb =5.6nf nf r c r r c drp fb fb fb drp 7.2 576 10*6.5) 110 162 ( ) ( 9 1 = ? + = ? + = ? = ? ? ? ? ? ? = ? ? ? ? ? = ? ? ? k v v r c l f r o ramp fb e e c cp 65.1 10*20 3.1 75.0* 162 )62 10*22()6/ 10* 100 ( ) 10* 140 2( ) 2( 3 6 9 23 2 nf r c l c cp e e cp 27 10 65.1 )62* 10*22()6/ 10* 100 ( 10 10 3 6 9 = ? ? ? = ? ? = ? ? choose c cp1 =47pf to reduce high frequency noise. current share loop compensation the crossover frequency of the current share loop f ci should be at least one decade lower than that of the voltage loop f c . choose the crossover frequency of current share loop f ci =3.5khz , and calculate c scomp , downloaded from: http:///
ir3081pbf page 33 of 40 10/01 /04 011 .0 )3.1 12(*)3.1 75.0 12( 75.0* 10* 800 * 10* 100 * 10*2.18 ) (*) ( * * * 3 12 3 = ? ? ? = ? ? ? = ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10*05.1* 2 *)] (* * * 2 1[* * * * * *65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? + = 6 4 4 6 3 3 10*05.1* 3500 2) 10*1.9* 105 33.1( 011 .0*] 105 ) 10*1.9* 105 33.1(*62* 10*22* 3500 * 2 1[*)6 10*5.0(*34* 105 *12* 10*2.18*65.0 ? ? ? ? + = ? ? ? ? nf 6.20 = choose c scomp =22nf downloaded from: http:///
ir3081pbf page 34 of 40 10/01 /04 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plane lgnd. ? connect the ground tab under the control ic to lgnd plane through a via. ? place the following critical components on the same layer as control ic and position them as close as possible to the respective pins, r osc , r ocset , r vdac , c vdac , c vcc , c ss/del and r cc/del . avoid using any via for the connection. ? place the compensation components on the same layer as control ic and position them as close as possible to eaout, fb and vdrp pins. avoid using any via for the connection. ? use kelvin connections for the remote voltage sense si gnals, vosns+ and vosns-, and avoid crossing over the fast transition nodes, i.e. switching n odes, gate drive signals and bootstrap nodes. ? control bus signals, vdac, rmpout, iin, vbias, and especially eaout, should not cross over the fast transition nodes. downloaded from: http:///
ir3081pbf page 35 of 40 10/01 /04 pcb metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. ? lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. the outboard extension ensure s a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? a single 0.30mm diameter via shall be placed in t he center of the pad land and connected to ground to minimize the noise effect on the ic. downloaded from: http:///
ir3081pbf page 36 of 40 10/ 01/04 solder resist ? the solder resist should be pulled away from the me tal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulli ng the s/r 0.06mm will alwa ys ensure nsmd pads. ? the minimum solder resist width is 0.13mm, theref ore it is recommended that the solder resist is completely removed from between the lead lands forming a single opening for each group of lead lands. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. ? the single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. downloaded from: http:///
ir3081pbf page 37 of 40 10/ 01/04 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, t he stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease t he incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3081pbf page 38 of 40 10/ 01/04 performance characteristics figure 13 - oscillator frequency versus rosc 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 rosc (k ohms) oscillator frequency (khz) figure 14 - ifb, bbfb, & ocset bias currents vs rosc 5 15 25 35 45 55 65 75 85 95 105 115 125 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 rosc (k ohm) ua figure 15 - vdac source & sink currents vc rosc (includes ocset bias current) 0 25 50 75 100 125 150 175 200 225 250 275 300 325 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 rosc (k ohm) ua isink isource figure 16 - bias current accuracy versus rosc (includes temperature and input voltage variation) 0% 2% 4% 6% 8% 10% 12% 14% 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 rosc (k ohm) +/-3 sigma variation (%) fb, bbfb, ocset bias current vdac sink current vdac source current downloaded from: http:///
ir3081pbf page 39 of 40 10/01 /04 package information 28l mlpq (5 x 5 mm body) C ja = 30 o c/w, jc = 3 o c/w data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa te l: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . downloaded from: http:///
ir3081pbf page 40 of 40 10/01 /04 www.irf.com downloaded from: http:///

▲Up To Search▲

Price & Availability of IR3081MPBF

	To Download IR3081MPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .